Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well-known etching technologies and subsequent deposition steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. Some integrated circuit manufacturers have developed electrochemical deposition techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers traditionally contained aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology has demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
A typical damascene or dual damascene process flow scheme for fabricating copper interconnects, such as copper lines and vias, typically includes: forming a trench pattern on a layer dielectric layer using an etch-resistant photoresist; etching a trench pattern; removing the photoresist; forming a via pattern on a dielectric material using etch resistant photoresist; etching vias; removing resist; depositing a tantalum barrier and a copper seed layer using PVD; electroplating copper to fill the etched features; and polishing copper off the wafer face leaving copper-filled interconnect circuitry.
As the number of levels in an interconnect technology is increased, the stacking of additional layers produces more rugged topography. Compounding this problem, electroplating bath additives are now commonly utilized to promote rapid “bottom-up” filling of high aspect-ratio features in damascene copper electroplating processes to ensure homogeneous metal fill of narrow features. Baths with “bottom-up” filling characteristics fill smaller features more rapidly than baths without such additives. Baths with “bottom-up” filling characteristics are designed to fill smaller features more rapidly than larger features. In some cases (e.g., plating baths with superior bottom-up filling characteristics and little or no leveling additives), plating continues at an accelerated rate after completing the small-feature filling stage. When many high-aspect ratio features are located in close proximity, a macroscopic raised area (series of bumps or a raised plateau) forms. This bump formation is also termed “feature overplating”.
The use of advanced “bottom-up” electrofilling techniques with wafers having low and high aspect-ratio features has created a problem of deposited metal surfaces with a wide range of topography, that is, topography containing both recessed and raised areas. Commonly, features vary in size by two orders of magnitude on a single layer. A 0.5 μm-deep feature can have widths of from 0.1 μm to 100 μm. Therefore, while electroplating is the preferred method of metalization, various aspects of improved plating regimens create challenging topography for subsequent planarization.
Chemical mechanical planarization (CMP) is one process used to remove excess material from a surface. It typically includes the use of a polishing pad and a solution containing an abrasive along with passivating agents and/or chemical agents that either retard or assist the planing of the material. CMP may be used for planing portions of wafers comprising dielectrics, such as silicon dioxide, or metals, such as copper, aluminum or tungsten. In copper CMP processes, excess copper is planed, or polished, off the top of the wafer surface to expose the thin pattern lines of copper metal inlaid within the barrier layer or substrate material. Polishing of the substrate is conducted until the underlying substrate is exposed, a condition commonly referred to as breakthrough. For copper CMP, breakthrough is defined as removal of metal from the top of the substrate until the underlying barrier layer or dielectric is first exposed. Breakthrough can be detected by optical reflectance from the substrate, by changes in polishing wheel temperature, by changes in polishing wheel torque, or by changes in chemical composition of used polishing solution. Once the excess copper is removed by the polishing step, the wafer must be cleaned with additional chemicals and soft pads to remove the abrasive particles that adhere to the wafer.
Metal polish slurries are designed to polish and to planararize conductive layers on semiconductor wafer substrates. The conductive layers are typically deposited on a dielectric layer and typically comprise metals such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), alloys thereof, semiconductor such as doped silicon (Si), doped polysilicon, and refractory metal silicides. The dielectric layer typically contains openings (e.g., vias and trenches) that are filled with the conductive material to provide a path through the dielectric layer to previously deposited layers and to circuit devices. After the conductive layer is polished, only the conductive material filling the features remains in the dielectric layer.
Metal polish slurries utilized for CMP of vias typically include very small particles (i.e., in a range of about from 20 to 1000 nm diameter) of the above-mentioned abrasive materials, suspended in a water-based liquid at a concentration of about from 1 to 7 weight percent. The pH may be acidic (i.e., <5) or neutral and is obtained and controlled by addition of acid(s) or salt(s) thereof. In addition to the organic acid(s) or salt(s), metal polishing slurries often include one or more oxidizing agents for assisting metal dissolution and removal, typically selected from hydrogen peroxide, potassium ferricyanide, ferric nitrate, or combinations thereof.
To create advanced semiconductor devices that contain multiple levels of metal lines in a dielectric requires the use of new dielectric materials. These new dielectric materials are commonly referred to as low-k dielectrics. Compared to traditional silicon dioxide dielectric, the newer low-k dielectrics are softer and less tough. The large downward pressure exerted onto a wafer during typical CMP polishing may damage fragile low-k dielectrics.
One approach to removing copper material from a substrate surface using CMP is called “overpolishing” the substrate. Overpolishing of some materials can result, however, in the formation of topographical defects, such as concavities or depressions in features, referred to as dishing. For example, an oxidizer can continue to etch electrically conductive material, for example, copper, during static periods when mechanical polishing is not being performed but the substrate surface remains in contact with the polishing slurry. This can occur, for example, upon completion of CMP but prior to removal of the substrate surface from contact with the slurry. As a consequence, unwanted static etching of the metallic features of the polished surface can occur, resulting in dishing. Dishing typically results in a height differential between the dielectric oxide layer and metalization features. Dishing is defined as removal of metal from the interconnect below the top level of the barrier layer. Dishing causes an increase in the electrical resistance of a copper interconnect because the conductor is thinner than it was designed to be. Increased resistivity can lead to overheating that causes the semiconductor device to fail.
Another problem of CMP processes is excessive removal of material from a wafer. The excessive removal of metal and barrier materials from a patterned substrate using slurry-based CMP is called erosion. Erosion typically manifests itself as a height differential between the height of a dielectric oxide layer in an open field region and its height in an array of metalization features. Erosion can lead to a non-planar topography across the wafer that can cause short circuits to form in subsequently deposited metal layers.
Additional problems of CMP include scratching of fine-lined metal in dielectric features by the agglomerations of abrasive particles. Scratching results in damage to interconnects and yield losses. A conglomerate of particles and gels can be removed from the slurries using point of use filtration prior to substrate polishing; however, plugging of the filters requires interruption of the process for filtrate removal, which is expensive and results in lower production. Conglomerate slurry particles also plug the surface of the polishing pad, and polishing pads must be periodically reconditioned in a non-value added step called dressing.
It is well-known in the art that CMP of copper is conducted by first oxidizing copper metal to an oxidized form of copper. The oxidized copper is then removed by exposing it to an electrolyte that dissolves the oxide material and by rubbing. Selectivity between the peak and valley of the surface may be achieved by the mechanical force exerted between the rotating wafer and the polishing pad to remove the oxide or protective layer. This method requires either large shear force and/or the presence of abrasives in order to achieve a reasonable removal rate, which may result in damage to the wafer, scratches, oxide erosion and copper dishing.
By planing metal-plated patterned surfaces down to an upper dielectric surface, only the portion of the material desired for conductive interconnects or for insulators remains. CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the endpoint can be difficult to detect. Also, CMP materials and equipment are expensive. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP. Also, with the introduction of low-k dielectrics into chip production, modification of traditional CMP processes is required, as current methods result in cracking and the lamination of most dielectric materials, which have a low compression strength and are fragile.
Other methods of planarization involve chemical etching techniques or electrochemical (electrolytic) etching techniques, such as electropolishing. Electrochemical planarization is an attractive alternative to CMP because it does not impart significant mechanical stresses to the workpiece, and consequently does not significantly reduce the integrity of the devices. Furthermore, electrochemical planarization is less likely to cause dishing, oxide erosion, and oxide loss of the dielectric layer. These techniques are low-cost methods, relative to CMP. Lower capital cost, easier waste handling, and much higher processing rates make them desirable alternatives to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. Electropolishing may be viewed as the reverse of electroplating. For example, U.S. Pat. No. 5,096,550, issued Mar. 17, 1992, to Mayer et al., teaches an electropolishing apparatus having a vessel filled with electrolytic solution, a cathode mounted in the vessel, and an anode containing the semiconductor substrate positioned in the vessel. U.S. Pat. No. 5,256,565, issued Oct. 26, 1993, to Bernhardt et al., teaches a method of forming a planarized metal interconnect by connecting a substrate containing a metal-filled trench or via to the anode of a DC voltage source, placing the substrate in an electrolyte, and flowing DC current through the substrate. United States Patent Application Publication No. 2004/0134793, published Jul. 15, 2004, by Uzoh et al., teaches a method and an apparatus for electroetching metal from a substrate surface by applying a voltage between an electrode and a substrate and continuously applying an etching solution to the substrate surface as a plurality of rollers are rotated.
A problem arises during the electropolishing of surfaces in which a large number of low aspect-ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low aspect ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the damascene layer so that the feature is completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles that resemble the original low aspect-ratio feature. The metal processes used to deposit the metal, which are substantially conformal over such low aspect-ratio features, are typically not continued to a point that would geometrically “close” such recesses, because to do so would require depositing a very thick metal layer. Depositing a thick metal layer would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low aspect ratio features are propagated and expanded to produce recesses that span the width of these features, leaving effectively little or no metal in the metal pad regions. Obviously this is an unacceptable result.
The term “electrochemical mechanical polishing” (ECMP) has been used in the prior art to refer to a group of various techniques for planarizing a metal layer on a semiconductor substrate. ECMP generally includes the application of a combination of electrochemical activity and mechanical activity to remove material from a substrate surface. For example, U.S. Pat. No. 6,811,680, issued Nov. 2, 2004, to Chen et al., teaches a method and an apparatus for planarizing a metal layer on a semiconductor substrate using ECMP including forming a passivation layer, and then sequentially conducting physical pad-polishing and electrochemical treatment in separate pad-polishing and electrochemical processing stations. U.S. Pat. No. 6,841,057, issued Jan. 11, 2005, to Wadensweiler et al., teaches a method and apparatus using ECMP for planarizing a metal layer of a substrate surface by holding the substrate face down in a polishing head and pressing the substrate against a conductive polishing pad while flowing electrolyte between the conductive polishing pad and an electrode, avoiding the use of conventional bias application such as wafer-edge contacts. Similarly, U.S. Pat. No. 6,776,693, issued Aug. 17, 2004, to Duboust et al. teaches a method and an apparatus in which a polishing head contains a cathode and a conductive polishing pad, and a face-up anodic substrate surface is pressed against the conductive polishing pad during electrochemical removal of material from the substrate. U.S. Pat. No. 6,821,409, issued Nov. 23, 2004, to Basol et al., teaches a method and an apparatus for planarizing metal on a substrate surface by using an electrolytic solution in combination with contacting, sweeping and/or polishing of the surface with an abrasive mask plate. Channels in the mask bring the electrolytic solution into contact with the substrate surface during electrochemical dissolution. U.S. Pat. No. 6,739,951, issued May 25, 2004, to Sun et al., together with U.S. Pat. No. 6,379,223, issued Apr. 30, 2002, to Sun et al., teach a method and an apparatus using ECMP that provide a non-abrasive polishing pad with an oxidizer-free non-abrasive electrolyte and apply a time-varying anodic potential to the workpiece surface for dissolving the metal while simultaneously applying mechanical polishing action to the surface. The polishing pad functions as a cathode. U.S. Pat. No. 6,066,030, issued May 23, 2000, to Uzoh, teaches a method and an apparatus for planarizing metal on a substrate surface by conducting electroetching followed by CMP using a single platform. U.S. Pat. No. 5,807,165, issued Sep. 15, 1998, to Uzoh et al., teaches a method of electrochemical mechanical planarization in which the entire surface of a substrate wafer is pressed against a polishing pad supported by a cathodic platen. United States Patent Application Publication No. 2004/0195111, published Oct. 7, 2004, by Talieh et al., teaches an apparatus useful for electroetching and polishing metal from a substrate surface that includes a conductive cathodic pad and conductive pins located in the pad to make electrical connection between an anode and the substrate surface. U.S. Pat. No. 6,790,130, issued Sep. 14, 2004, to Doan et al., teaches a ECMP method in which a conductive polishing pad serves as an electrode during simultaneous electrochemical and physical polishing operations. U.S. Pat. No. 6,706,158, issued Mar. 16, 2004, to Sharan et al., teaches a ECMP apparatus in which a conductive polishing pad serves as cathode during electrochemical and physical polishing operations.
There exists a need in the semiconductor industry to polish thin metal films and fine copper interconnect lines inlaid on a patterned substrate that includes dielectric and barrier layer materials. The metal films and interconnect lines and patterns revealed by polishing should be substantially free from scratches, dishing and erosion. The techniques for polishing fine copper interconnect lines and metal films on a patterned substrate should yield smooth surfaces, have a high removal rate, and applied a low pressure to substrate surfaces. It is further desirable to be able to control the removal rate of the metal from the substrate without changing pressure or rotational rate of a polishing pad or substrate. What is needed therefore is improved electropolishing technology for planarizing conductive layers having varying topography, particularly metal layers having both recesses and raised regions and having both very narrow (submicron) and very wide (on the order of 100 μm) widths.